DLP-RFS1280 2.4GHz LORA RF Transceiver Module with Modular Certification
December 2017 (Updated May 2018): DLP Design, Inc. is pleased to announce the DLP-RFS1280pre-certified module based on the SX1280 transceiver chip from Semtech Corporation. This new module implements the Semtech SX1280 transceiver, and is designed to work with an external, user-supplied microcontroller.
The feature set for this module includes:
FCC / IC / RED / MIC Modular Certifications in Place
On-Board Chip Antenna
U.FL Connector for External, User-Supplied Antenna
+11.5dBm Transmit Power
-131dBm Receive Sensitivity
<5.5mA Receive Current
Surface or Through-Hole Mount, 2x2.3cm Footprint
Also announced today, the DLP-RFS1280ACT demonstration platform has the following features:
Simple Pairing Method with Other Transceiver
Fully-Commented Demonstration C Source Code
Low-Power NUCLEO-L073RZT6 Microcontroller Development Board
Ranging (Distance-Measurement) Demonstration in Meters/Feet
Lighted LCD Display
Speaker/Microphone for Walkie-Talkie (Push-To-Talk) Demonstration
Whip Antenna
Internal/External Antenna Selection
Easy Mode Selection (LORA/FLRC/GFSK)
Long-Range Ping Test
CW and Modulated CW Settings
Internal/External Antenna Selection during Demonstrations
Running on the STMicroelectronics STM32L073RZ microcontroller, this demonstration platformrequires less than 55K of FLASH program memory to perform all of its functions.
Download the DLP-RFS1280 datasheet.
Just Announced: The DLP-RFS-LOCATOR demonstrates an implementation of the DLP-RFS1280 module whereby lost items can be found using both the Ranging (distance-measurement) feature of the SX1280 as well as a high-gain Yagi antenna for determining the direction to the lost item. For this demonstration, the DLP-RFS1280ACT serves as the 'lost item', and its location (both distance and direction) is determined by the DLP-RFS-LOCATOR wand.
TI DLP Pico Technology for Aftermarket Head-up Displays 1 Introduction A head-up display (HUD) is a transparent display that superimposes rich, configurable, real-time data in a driver's normal line of sight. This training curriculum details the use of DLP® technology for automotive head-up display and transparent window display (TWD) applications. Driver required for DLP PICO PROJECTOR? How to check projector detect or not? Regards, Pratik Kothari. Locked; Cancel Genius 9935 points Pascal DLP May 11, 2011 3:45 PM; In reply to pratik kothari: Hello Pratik, The Pico Kit v2 contains an EDID chip which reports to the computer its name and resolution and frame rate requirements (which is.
DLP-RFS1280 | DLP-RFS1280ACT* | DLP-RFS-LOCATOR* More Info |
The DLP-RFS1280 is available from our distribution network. | The DLP-RFS1280ACT is available from our distribution network. | The DLP-RFS-LOCATOR is available from our distribution network. |
DLP-PMV Hands-Free Voltmeter
DLP Design, Inc. is pleased to announce the new PROTOMETER® voltmeter.
The PROTOMETER (Part Number: DLP-PMV) frees your hands and helps control clutter on your workbench as you test and modify the circuitry on your breadboard. No more having to hold voltmeter test leads to monitor DC or AC (RMS) voltages - simply plug a PROTOMETER into your breadboard and turn it on. Voltages up to 60V are displayed on the miniature LCD display. The PROTOMETER is powered by a single coin cell, and it is small enough to accommodate multiple meters monitoring multiple voltages on even a small breadboard.
Download the DLP-PMV owner's manual for more details.
The DLP-PMV is available from our distribution network. |
Introduction
Drivers Ti Dlp Drivers
The PCI Express (PCIe) module is a multi-lane I/O interconnect providinglow pin count, high reliability, and high-speed data transfer at ratesof up to 8.0 Gbps per lane per direction. It is a 3rd Generation I/O Interconnecttechnology succeeding ISA and PCI bus that is designed to be used as ageneral-purpose serial I/O interconnect in multiple market segments,including desktop, mobile, server, storage and embedded communications.
Features of J7ES
There are four instances of the PCIe subsystem. Following are some of themain features:
- Each instance can be configured to operate in Root Complex mode orEnd Point mode
- One or two lane configuration, capable up to 8.0 Gbps/lane (Gen3)
- Support for Legacy, MSI and MSI-X Interrupt
- There can be 32 different address mappings in outbound address translationunit. The mappings can be from regions reserved for each PCIe instance.
- For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
- 128 MB region with address in lower 32 bits
- 4 GB region with address above 32 bits
- For instance PCIE2 and PCIE3, there are two regions in SoC Memory Map:
- 128 MB region with address above 32 bits
- 4 GB region with address above 32 bits
- For instance PCIE0 and PCIE1, there are two regions in SoC Memory Map:
Capabilities of J721E EVM
There are three instances of the PCIe subsystem on the EVM. Following aresome of the details for each instance:
| Instance | Supported lanes | Supported Connector |
|---|---|---|
| PCIE0 | 1 lane | Standard female connector |
| PCIE1 | 2 lane | Standard female connector |
| PCIE2 | 2 lane | m.2 connector keyed for SSD (M key) |
Drivers Ti Dlp 65
Hardware Setup Details
Drivers Ti Dlp Screen
J721E is, by default, intended to be operated inRoot Complex mode.
For End Point mode, PCIE_1L_MODE_SEL (switch 5) and PCIE_2L_MODE_SEL (switch 6)should be set to ‘0’.
Ti Dlp Chip
RC Software Architecture
Following is the software architecture for Root Complex mode:
Following is a brief explanation of layers shown in the diagram:
- There are different drivers for the connected PCIe devices likepci_endpoint_test, tg-3, r8169, xhci-pci, ahci, etc. It could bevendor-specific like most of the ethernet cards (tg3, r8169) or class-specificlike xhci-pci and ahci. Each of these drivers will also interact with it’s owndomain-specific stack. For example, tg3 will interface with network stack, andxhci-pci will interface with USB stack.
- The PCI core layer scans the PCIe bus to identify and detect any PCIe devices.It also binds the driver from the layer above, for the PCIe device, based onvendorid, deviceid and class.
- The PCI BIOS layer handles resource management. For example, allocation ofmemory resources for BARs.
- The bottom-most layer consists of the PCIe platform drivers like pcie-cadence,pcie-designware, etc. pci-j721e and pci-dra7xx are TI’s wrappers over thesedrivers. They configure platform-specific controllers and performactual register writes.
RC Device Configuration
DTS Modification
The default dts is configured to be used in root complex mode.
Linux Driver Configuration
The following config options have to be enabled in order to configure thePCI controller to be used in Root Complex mode.
Testing Details
The RC should enumerate any off-the-shelf PCIe cards. It has been testedwith Ethernet cards, NVMe cards, PCIe USB card, PCIe WiFi card, PCIe SATAcard and also to J721E in loopback mode.
In order to see if the connected card is detected, lspci utility should beused. Different utilities can be used depending on the cards.
Following are the outputs for some of them:
Loopback mode (J721E EVM to J721E EVM)
Two J721E EVMs can be connected in loopback mode by following the stepsexplained inEnd Point (EP) Device Configurationsection for End Point (EP) andHOST Device Configurationsection for Root Complex (RC) inPCIe End Point documentation. The pci-epf-testdriver will be configured for End Point(EP) using those steps.
The lspci output on the Root Complex (RC) device is as follows:
WiFi card
- lspci output
- Test using ping
NVMe SSD
- lspci output
- Test using hdparm
- Test using dd